This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report.
RocketChip development meetings happen every 2 weeks on Wednesday 17:00 – 18:00am CST (Pacific Time - Los Angeles) with meeting notes here:
- Click here to subscribe Meeting Schedule(iCal format)
- Click here to view Meeting Schedule via Google Calendar
- Click here to join Zoom meeting (ID: 93899365000, passcode: 754340)
For possible time adjustments, they will be negotiated in Slack and published in the calendar.
- Quick instructions for those who want to dive directly into the details without knowing exactly what's in the repository.
- What's in the Rocket chip generator repository?
- How should I use the Rocket chip generator?
- How can I parameterize my Rocket chip?
- Debugging with GDB
- Building Rocket Chip with an IDE
- Contributors
$ git clone https://github.com/ucb-bar/rocket-chip.git
$ cd rocket-chip
$ git submodule update --init
You may need to install some additional packages to use this repository. Rather than list all dependencies here, please see the appropriate section of the READMEs for each of the subprojects:
Generating verilog
$ make verilog
Generating verilog for a specific Config
$ make verilog CONFIG=freechips.rocketchip.system.DefaultSmallConfig
If you are trying to keep your repo up to date with this GitHub repo, you also need to keep the submodules and tools up to date.
$ # Get the newest versions of the files in this repo
$ git pull origin master
$ # Make sure the submodules have the correct versions
$ git submodule update --init --recursive