Copyright 2012-2026 / Enjoy-Digital & LiteX developers

The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create full FPGA based systems.

LiteX SoC builder framework quick tour/overview: Slides

Want to get started and/or looking for documentation? Make sure to visit the Wiki!

Want development notes from building FPGA SoCs with LiteX? Visit the LiteX Notes blog!

A question or want to get in touch? Join us on Discord or on our IRC channel: [#litex at irc.libera.chat].

LiteX provides all the common components required to easily create an FPGA Core/SoC:

• ✔️ Buses and Streams (Wishbone, AXI, Avalon-ST) and their interconnect.
• ✔️ Simple cores: RAM, ROM, Timer, UART, JTAG, etc….
• ✔️ Complex cores through the ecosystem of cores: LiteDRAM, LitePCIe, LiteEth, LiteSATA, etc...
• ✔️ Various CPUs & ISAs: RISC-V, OpenRISC, LM32, Zynq, X86 (through a PCIe), etc...
• ✔️ Mixed languages support with VHDL/Verilog/(n)Migen/Spinal-HDL/etc... integration capabilities.
• ✔️ Powerful debug infrastructure through the various bridges and Litescope.
• ✔️ Direct/Fast simulation through Verilator.
• ✔️ Build backends for open-source and vendors toolchains.
• ✔️ And a lot more... :)

• More ways to build SoCs: Intel Cyclone V/Agilex HPS integration, Gowin AE350 improvements, native AXI/AXI-Lite HyperRAM, and broader framebuffer memory support.
• New hardware building blocks: FPGA temperature monitors, AP Memory PSRAM and Gowin HyperRAM, SPI/parallel LCD, OV5640 camera capture, and I2S audio.
• Better connectivity: packet streams with byte-valid final words, new LiteEth 1000BASE-X/SGMII PHY options, and LitePCIe protocol and DMA improvements.
• More boards and targets, including ModRetro M64/Chromatic, Sipeed Tang Mega 60K, and new Cyclone V/Agilex HPS paths.
• A dedicated release helper and PyPI publishing workflow for the LiteX ecosystem.

See CHANGES.md for the full list of fixes, additions, and ecosystem updates. LiteJESD204B has been renamed to