logisim-evolution
+33Digital logic design tool and simulator
verilog
Chủ đề #verilog trên GitHub — repository trong kho Beeknoee có gắn topic này.
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Repository trong #verilog
edge-cores
+17The shortest path from PyTorch to custom ASICs.
OpenROAD
+18OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
google/xls
+12XLS: Accelerated HW Synthesis
verilator
+12Verilator open-source SystemVerilog simulator and lint system
cocotb/cocotb
+7cocotb: Python-based chip (RTL) verification
hdl
+6HDL libraries and projects
chisel
+5Chisel: A Modern Hardware Design Language
openwifi
+5open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
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